At the IDS Lab, our active research areas encompass a wide range of cutting-edge technologies in the field of digital VLSI and architecture. We are currently focused on the following areas:

Neural Processing Units

Our research in neural processing units (NPUs) explores the design and implementation of hardware architectures optimized for machine learning and other types of artificial intelligence. Our goal is to develop NPUs that can provide high-performance and energy-efficient processing for a wide range of applications, from natural language processing to computer vision and beyond. Through our research, we aim to push the boundaries of what's possible in intelligent systems and to enable new breakthroughs in the field of AI.

Neuromorphic Computing

Our research in neuromorphic computing explores the use of hardware architectures inspired by the structure and function of the human brain. By leveraging the principles of neural networks and other brain-inspired algorithms, we aim to develop new computing paradigms that can provide higher performance, energy efficiency, and fault tolerance compared to traditional computing architectures. Our work in this area has the potential to transform the way we approach computing and enable new breakthroughs in a wide range of applications, from robotics to natural language processing.

Application-Specific Accelerators for Machine Learning

Our research in application-specific accelerators for machine learning focuses on developing specialized hardware architectures that can accelerate specific types of machine learning algorithms. By tailoring our designs to the unique demands of each application, we can achieve significant improvements in performance, energy efficiency, and accuracy compared to more general-purpose architectures. Our research in this area has the potential to revolutionize the way we approach machine learning and unlock new possibilities for a wide range of applications.

Hardware-based SAT Solvers

Our research in hardware-based SAT solvers explores the use of specialized hardware architectures to solve the Boolean satisfiability problem (SAT), which is a fundamental problem in computer science with many practical applications. By leveraging the massive parallelism and energy efficiency of hardware-based approaches, we aim to develop SAT solvers that can solve large and complex instances of the problem with unprecedented speed and efficiency. Our work in this area has the potential to unlock new possibilities in automated reasoning, verification, and other fields.