The IDS Lab is committed to advancing the frontiers of digital VLSI and architecture through our cutting-edge research and collaboration with other experts in the field. We are proud to have published a wide range of papers in top-tier conferences and journals, showcasing our expertise in a variety of areas. Here are some of our recent publications:

Top-Tier Conference Proceedings

• S. Lee, D. Nam, and J.Park, “RGHT-Q: Large Language Model Accelerator with Reconfigurable General-Matrix-Multiplication for Heterogeneous-Homogeneous Tensor Quantization”, Design Automation and Test in Europe (DATE), accepted
• S. Lee, J. Park, and D. Jeon, “A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array,” IEEE European Solid-State Circuits Conference (ESSCIRC), 2023
• S. Park, S. Lee, J. Park, H.-S. Choi, and D. Jeon, “A 0.81mm2 740µW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), 2023.
• S. Jeong, J. Park, and D. Jeon, “A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training,” IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
• S. Lee, J. Park, and D. Jeon, “Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization,” International Conference on Learning Representations (ICLR), 2022.
• S. Woo, J. Park, J. Hong, and D. Jeon, “Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection,” Conference on Neural Information Processing Systems (NeurIPS), 2021.
• J. Park*, S. Lee*, and D. Jeon, “A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree,” IEEE International Solid-State Circuits Conference (ISSCC), 2021. (*Equal Contribution)
• J. Park, J. Lee, and D. Jeon, “A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback,” IEEE International Solid-State Circuits Conference (ISSCC), 2019.

Journal Publications

• S. Park, S. Lee, J. Park, H.-S. Choi, K. Lee, and D. Jeon, “A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), accepted.
• J. Park, S. Lee, and D. Jeon, “A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees,” IEEE Journal of Solid-State Circuits (JSSC), 2022.
• J. Park, J. Lee, and D. Jeon, “A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback,” IEEE Journal of Solid-State Circuits (JSSC), 2020, invited.